1. Field of the Invention
The present invention relates to interface circuits, i.e., those circuits through which exchange of digital signals between data processing equipment is achieved. More particularly, the present invention relates to interface circuits in accordance with international standards, such as the Electrical Industry Association (EIA) RS 232C or the Comite Consullatif International des Telecommunications (CCITT) V 24 standards.
2. Description of the Problem and Prior Art
Owing to the existence of design standards, such as the EIA or CCITT standards, equipment from different origins, i.e. manufacturers, may readily be interconnected. These interface circuits have, therefore, a capital function and are widely used to link different types of data processing equipment together, as for example, a terminal (or a multiplexer, or a processor) to a modem, or the like. The EIA standards define the interchange procedures and electrical characteristics of the signals (voltages, impedances, etc.).
In the EIA RS 232C and/or the CCITT V24 standards to which the present invention is concerned, the binary signals are quite different from those existing inside the machines and are unrelated to any of the known technologies, such as, TTL (Transistor-Transistor Logic), ECL (Emitter-Coupled-Logic), etc. The signal characteristics for these standards are defined in the following paragraphs.
The positive voltage level range of the interface circuit must lie between +5 and +15 volts. Likewise, the negative voltage level range must lie between -5 and -15 volts. The prohibited range is the -3 V to +3 V zone which, of course, includes 0 volts. Signals should not lie in this prohibited range at anytime. The impedance at the input of the circuit receivers must be resistive, with 3k.OMEGA..ltoreq.R.ltoreq.7k.OMEGA..
The interface circuit output voltage during transitions from high voltage state to low voltage state should vary at a well-defined rate within closely specified maximum and minimum levels in order to obtain signals with a sufficiently high rate while avoiding the well-known crosstalk phenomena caused by slew rates too steep. The slew-rate (.DELTA.v/.DELTA.t) of the output signal should be comparatively independent (within given limits) of the load applied to the output.
In addition, the interface circuit must withstand an accidental misconnection at any voltage within -15 volts to +15 volts and not be the cause of excessively high currents that might cause connecting cable or equipment destruction. This applies to the interface circuit being "powered on" as well as being "powered off". Means should be provided to prevent erratic signals from being transmitted to the output at the time the circuit is turned on. Additionally, a high impedance state is desirable for parallel applications (the so-called tristate mode). When the interface circuit is not powered, the circuit output should present an impedance equal to, at least, 300.OMEGA..
A large variety of interface circuits are known in the prior art with a considerable number commercially available. Such prior art circuits are particular to an application, relatively simple and cheap but, unfortunately, have a number of significant drawbacks. For example, prior art interface circuits exhibit low density; very often there are only two interface circuits per module.
Typically, components external to the integrated interface circuits are necessary to fulfill auxiliary functions, e.g. to control the slew rate (capacitor), protect against possible overvoltages (diodes), remove erratic signals at the time the circuit is turned on, etc.
Likewise, these circuits typically require high supply voltages (e.g. .vertline.V.sub.CC .vertline..gtoreq.12 volts) while the present tendency is to use lower supply voltages. As is understood, a lower voltage (8 volts, for instance) is of advantage in terms of electrical comsumption and thermal dissipation but is not compatible with the requirement of having voltage magnitudes greater than +5 volts and -5 volts. In addition, during interface circuit power on, it is necessary that power supplies be set according to a special sequence to avoid erratic signal problems. This is necessary because output currents are not high enough to drive several and/or long connecting cables.
A typical interface circuit (line driver) and its characteristics is described in the handbook entitled "The Integrated Circuits Catalog for Design Engineers", First Edition, Texas Instruments Inc., at pages 3-149 through 3-152. It should be noted that this circuit is not compatible with all the logic families as, for example, ECL logic. It is also noted that the slew rate control is accomplished by an external capacitor and, thus, the circuit requires adaptation for each particular case (line, customer, etc.). The Texas Instrument circuit also requires high supply voltages (.+-.12 volts) and cannot be used in the "tristate" mode. Finally, this circuit demands a high supply current.